FIG. 1 shows conventional sense amplifier circuitry for a semiconductor memory device comprising a sense amplifier 10, first and second multiplexers 20 and 30 on opposite sides of the sense amplifier 10, and restore circuits 40 and 50 also on opposite sides of the sense amplifier 10. The restore circuits 40 and 50 are also known as equalization circuits because they precharge and equalize (i.e., “restore”) voltage on the bitlines (BLs) to which they connect. The sense amplifier 10 is connected to memory storage cells on one side, called the “t” side, when it is connected to bitline pairs (comprised of a BL and BL complement) 60 and 62. Similarly, the sense amplifier 10 is connected to memory cells on the other side, called the “b” side, when it is connected to BL pairs 70 and 72. Multiplexer 20 controls the connection of the sense amplifier 10 to BL pairs 60 and 62 when memory cells on the “t” side are to be accessed and multiplexer 30 controls connection of the sense amplifier 10 to BL pairs 70 and 72 when memory cells on the “b” side are to be accessed.
The restore circuits 40 and 50 ensure that their associated BLs are precharged to the correct voltage and that the voltages on the BL and BL complement lines in a BL pair are equalized within a suitable time period. For each BL pair on the “t” side, restore circuit 40 includes two charging transistor pairs 42 connected to the BL and BL complement nodes, and an equalization transistor 44 connected across the BL and BL complement nodes. The transistor pairs 42 are activated by a restore control signal called EQLt. Similarly, for each BL pair on the “b” side, restore circuit 50 includes two charging transistor pairs 52 connected to the BL and BL complement nodes, and an equalization transistor 54 connected across the BL and BL complement nodes. The charging transistor pairs 52 are activated by a restore control signal called EQLb. An additional enhancement mode leakage limiting transistor is provided for each of the restore circuits, shown at 90 for restore circuit 40 and at 92 for restore circuit 50. In one example, the transistors 90 and 92 are enhancement mode type transistors. The drains of the transistors 90 and 92 are connected to a voltage source, called VBLEQ, and the gates of the transistors 90 and 92 are connected to a voltage called VINT. The source of each of the transistors 90 and 92 are connected to the pair of charging transistors in the restore circuits 40 and 50, respectively. The control signals shown for the sense amplifier 10 are known and one with ordinary skill in the art would understand their operation.
The transistors 90 and 92 perform both a voltage regulation function and a leakage current limiting function. The voltage regulation function involves supplying a sufficient amount of current from the voltage reference source VBLEQ to bring the BLs of a BL pair to the proper voltage in a required amount of time. This time is usually short and occurs at the beginning of a precharge period when an array activation is concluded. The leakage current limiting function involves maintain the voltage levels on the BL's that have been established at the beginning of the precharge period while also preventing excessive current from flowing from voltage reference source to the BLs in the event there is a BL leakage anomaly causing a short-circuit between a BL and a wordline (WL) in that part of the memory array. This function is relevant to the time period after the BL's have been initially precharged and equalized. When transistors 90 and 92 are sized to perform the voltage regulation function well the current level they can limit to in the event of a short becomes too high for low power DRAM applications. Conversely, when transistors 90 and 92 are sized for a sufficiently low limiting current the resulting regulation current level is too low to regulate BL voltage level adequately during the initial precharge and equalization.
FIG. 2 shows another type of conventional sense amplifier circuitry for a semiconductor memory device. In this example, enhancement mode leakage limiting transistors previously associated with the restore circuits 40 and 50 are changed to depletion mode transistors 100 and 102. The gate and source of each of the transistors 100 and 102 are connected together, and to the pair of charging transistors in their respective restore circuits 40 and 50, respectively. The drains of transistors 100 and 102 are connected to the voltage source VBLEQ. With transistors 100 and 102 configured in this way they have a saturation characteristic. As voltage across the transistor is increased, it reaches a limiting saturation current. When transistors 100 and 102 are sized to perform the voltage regulation function well the current level they can limit to in the event of a short is lower than the limiting current that results with using an enhancement mode transistor. This lower limiting current level is an improvement over the use of an enhancement mode limiting transistor but still results in too high of a leak current for low power DRAM applications. Conversely, when transistors 100 and 102 are sized for a sufficiently low limiting current the resulting regulation current level is still too low to regulate BL voltage level adequately during an initial precharge period.
Because of the inherent conflict between regulation requiring a larger current level for a short duration and a current limiting characteristic requiring a lower current level over a long duration it is undesirable to provide one transistor device to perform both voltage regulation and leakage current reduction functions simultaneously.